The invention relates to tester systems.
Tester systems for electronic devices (for example, integrated circuit devices such as memory devices, microcontrollers, and microprocessors) have increasingly become more sophisticated as the electronic devices themselves become more complex. In addition to complexity of functionality, the speeds at which electronic devices can operate have also increased dramatically.
One type of electronic device is the memory device, including dynamic random access memories (DRAMS), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), and other memory products. It is not uncommon for these memory devices to run at frequencies at or greater than 100 MHz.
To test at such high frequencies, tester systems include a clock running at or above the maximum frequency at which devices can be tested. However, as clock frequencies increase, factors such as skewing, signal line delays, and gate propagation delays become significant. In addition, because of the different paths of signals to and from a device under test, there may be variations in skewing, signal line delay, and gate propagation delay between signals of the device under test. To compensate for such variations, some tester systems, such as production-oriented automatic test equipment (ATE) testers, use very high frequency clocks (some as high as 500 MHz) to provide very fine resolutions. In these systems, during tester start-up, variations in signal paths can be calibrated by adjusting signal path timings. Such testers, however, require sophisticated internal circuitry and signal paths to operate at the desired high frequencies, which can result in a very high cost system.